IEEE Computer Architecture Letters

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#	Title	Journal	Year	Citations
1	DRAMSim2: A Cycle Accurate Memory System Simulator	IEEE Computer Architecture Letters	2011	696
2	Ramulator: A Fast and Extensible DRAM Simulator	IEEE Computer Architecture Letters	2016	342
3	MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research	IEEE Computer Architecture Letters	2002	254
4	NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems	IEEE Computer Architecture Letters	2015	172
5	gem5-gpu: A Heterogeneous CPU-GPU Simulator	IEEE Computer Architecture Letters	2015	161
6	Subtleties of transactional memory atomicity semantics	IEEE Computer Architecture Letters	2006	156
7	Fast Bulk Bitwise AND and OR in DRAM	IEEE Computer Architecture Letters	2015	134
8	Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management	IEEE Computer Architecture Letters	2012	117
9	Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors	IEEE Computer Architecture Letters	2006	108
10	Power Management of Datacenter Workloads Using Per-Core Power Gating	IEEE Computer Architecture Letters	2009	106
11	LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory	IEEE Computer Architecture Letters	2017	90
12	Cache-aware Roofline model: Upgrading the loft	IEEE Computer Architecture Letters	2014	89
13	Exploiting Internal Parallelism of Flash-based SSDs	IEEE Computer Architecture Letters	2010	87
14	DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator	IEEE Computer Architecture Letters	2020	87
15	Corollaries to Amdahl's Law for Energy	IEEE Computer Architecture Letters	2008	80
16	ParMiBench - An Open-Source Benchmark for Embedded Multiprocessor Systems	IEEE Computer Architecture Letters	2010	79
17	Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures	IEEE Computer Architecture Letters	2003	77
18	Many-Core vs. Many-Thread Machines: Stay Away From the Valley	IEEE Computer Architecture Letters	2009	77
19	Logic-Based Distributed Routing for NoCs	IEEE Computer Architecture Letters	2008	73
20	Architectural Support for Mitigating Row Hammering in DRAM Memories	IEEE Computer Architecture Letters	2015	71
21	Resistive Associative Processor	IEEE Computer Architecture Letters	2015	68
22	The Architectural Implications of Cloud Microservices	IEEE Computer Architecture Letters	2018	67
23	UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development	IEEE Computer Architecture Letters	2007	65
24	Flattened Butterfly Topology for On-Chip Networks	IEEE Computer Architecture Letters	2007	61
25	Heterogeneity in “Homogeneous” Warehouse-Scale Computers: A Performance Opportunity	IEEE Computer Architecture Letters	2011	59
26	Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs	IEEE Computer Architecture Letters	2009	57
27	Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example	IEEE Computer Architecture Letters	2002	56
28	Globally Adaptive Load-Balanced Routing on Tori	IEEE Computer Architecture Letters	2004	56
29	An FPGA-based In-Line Accelerator for Memcached	IEEE Computer Architecture Letters	2014	53
30	An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori	IEEE Computer Architecture Letters	2004	50
31	Efficient In-Memory Processing Using Spintronics	IEEE Computer Architecture Letters	2018	49
32	Worst-case Traffic for Oblivious Routing Functions	IEEE Computer Architecture Letters	2002	47
33	Fairness Metrics for Multi-Threaded Processors	IEEE Computer Architecture Letters	2011	47
34	Orbital Edge Computing: Machine Inference in Space	IEEE Computer Architecture Letters	2019	47
35	A Phase Change Memory as a Secure Main Memory	IEEE Computer Architecture Letters	2010	46
36	Systolic Tensor Array: An Efficient Structured-Sparse GEMM Accelerator for Mobile CNN Inference	IEEE Computer Architecture Letters	2020	46
37	Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links	IEEE Computer Architecture Letters	2002	43
38	A Deep Q-Learning Approach for Dynamic Management of Heterogeneous Processors	IEEE Computer Architecture Letters	2019	43
39	An Energy-Efficient Processor Architecture for Embedded Systems	IEEE Computer Architecture Letters	2008	42
40	On Estimating Optimal Performance of CPU Dynamic Thermal Management	IEEE Computer Architecture Letters	2003	41
41	Circuit-Switched Coherence	IEEE Computer Architecture Letters	2007	41
42	A High-Throughput Distributed Shared-Buffer NoC Router	IEEE Computer Architecture Letters	2009	40
43	Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture	IEEE Computer Architecture Letters	2008	39
44	Counter-Based Tree Structure for Row Hammering Mitigation in DRAM	IEEE Computer Architecture Letters	2017	39
45	SmartSSD: FPGA Accelerated Near-Storage Data Analytics on SSD	IEEE Computer Architecture Letters	2020	39
46	An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation	IEEE Computer Architecture Letters	2006	38
47	Stripes: Bit-Serial Deep Neural Network Computing	IEEE Computer Architecture Letters	2017	37
48	User-Driven Frequency Scaling	IEEE Computer Architecture Letters	2006	36
49	Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal	IEEE Computer Architecture Letters	2008	36
50	Spatial Correlation and Value Prediction in Convolutional Neural Networks	IEEE Computer Architecture Letters	2019	36

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