IEEE Transactions on Semiconductor Manufacturing

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#	Title	Journal	Year	Citations
1	Scheduling semiconductor wafer fabrication	IEEE Transactions on Semiconductor Manufacturing	1988	565
2	Material removal mechanism in chemical mechanical polishing: theory and modeling	IEEE Transactions on Semiconductor Manufacturing	2001	498
3	Fifty Years of Moore's Law	IEEE Transactions on Semiconductor Manufacturing	2011	432
4	A Convolutional Neural Network for Fault Classification and Diagnosis in Semiconductor Manufacturing Processes	IEEE Transactions on Semiconductor Manufacturing	2017	347
5	Efficient scheduling policies to reduce mean and variance of cycle-time in semiconductor manufacturing plants	IEEE Transactions on Semiconductor Manufacturing	1994	346
6	Fault Detection Using the k-Nearest Neighbor Rule for Semiconductor Manufacturing Processes	IEEE Transactions on Semiconductor Manufacturing	2007	345
7	VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects	IEEE Transactions on Semiconductor Manufacturing	2008	313
8	Closed-loop job release control for VLSI circuit manufacturing	IEEE Transactions on Semiconductor Manufacturing	1988	308
9	Run by run process control: combining SPC and feedback control	IEEE Transactions on Semiconductor Manufacturing	1995	280
10	The use and evaluation of yield models in integrated circuit manufacturing	IEEE Transactions on Semiconductor Manufacturing	1990	273
11	Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network	IEEE Transactions on Semiconductor Manufacturing	2018	272
12	Modeling, analysis, simulation, scheduling, and control of semiconductor manufacturing systems: A Petri net approach	IEEE Transactions on Semiconductor Manufacturing	1998	257
13	Scheduling analysis of time-constrained dual-armed cluster tools	IEEE Transactions on Semiconductor Manufacturing	2003	243
14	A steady-state throughput analysis of cluster tools: dual-blade versus single-blade robots	IEEE Transactions on Semiconductor Manufacturing	1997	213
15	Supervisory run-to-run control of polysilicon gate etch using in situ ellipsometry	IEEE Transactions on Semiconductor Manufacturing	1994	206
16	Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets	IEEE Transactions on Semiconductor Manufacturing	2015	197
17	A Petri Net Method for Schedulability and Scheduling Problems in Single-Arm Cluster Tools With Wafer Residency Time Constraints	IEEE Transactions on Semiconductor Manufacturing	2008	194
18	Modeling of chemical-mechanical polishing: a review	IEEE Transactions on Semiconductor Manufacturing	1995	191
19	A neural-network approach to recognize defect spatial pattern in semiconductor fabrication	IEEE Transactions on Semiconductor Manufacturing	2000	189
20	Analysis and decomposition of spatial variation in integrated circuit processes and devices	IEEE Transactions on Semiconductor Manufacturing	1997	185
21	Thermal and stress analysis of semiconductor wafers in a rapid thermal processing oven	IEEE Transactions on Semiconductor Manufacturing	1988	181
22	A production planning methodology for semiconductor manufacturing based on iterative simulation and linear programming calculations	IEEE Transactions on Semiconductor Manufacturing	1996	181
23	Single-wafer cluster tool performance: an analysis of throughput	IEEE Transactions on Semiconductor Manufacturing	1994	178
24	Modeling of interconnect capacitance, delay, and crosstalk in VLSI	IEEE Transactions on Semiconductor Manufacturing	2000	176
25	Advantages of plasma etch modeling using neural networks over statistical techniques	IEEE Transactions on Semiconductor Manufacturing	1993	174
26	Dynamic batching heuristic for simultaneous processing	IEEE Transactions on Semiconductor Manufacturing	1991	172
27	Convolutional Neural Network for Wafer Surface Defect Classification and the Detection of Unknown Defect Class	IEEE Transactions on Semiconductor Manufacturing	2019	172
28	Multiblock Principal Component Analysis Based on a Combined Index for Semiconductor Fault Detection and Diagnosis	IEEE Transactions on Semiconductor Manufacturing	2006	166
29	Classification of Mixed-Type Defect Patterns in Wafer Bin Maps Using Convolutional Neural Networks	IEEE Transactions on Semiconductor Manufacturing	2018	154
30	In Search of “Forever,” Continued Transistor Scaling One New Material at a Time	IEEE Transactions on Semiconductor Manufacturing	2005	151
31	Ring Oscillators for CMOS Process Tuning and Variability Control	IEEE Transactions on Semiconductor Manufacturing	2006	150
32	Effects of abrasive size distribution in chemical mechanical planarization: Modeling and verification	IEEE Transactions on Semiconductor Manufacturing	2003	143
33	Integrated circuit yield management and yield analysis: development and implementation	IEEE Transactions on Semiconductor Manufacturing	1995	142
34	Scheduling of semiconductor test facility via Petri nets and hybrid heuristic search	IEEE Transactions on Semiconductor Manufacturing	1998	139
35	Single-wafer cluster tool performance: an analysis of the effects of redundant chambers and revisitation sequences on throughput	IEEE Transactions on Semiconductor Manufacturing	1996	137
36	Tractable Nonlinear Production Planning Models for Semiconductor Wafer Fabrication Facilities	IEEE Transactions on Semiconductor Manufacturing	2006	136
37	A Voting Ensemble Classifier for Wafer Map Defect Patterns Identification in Semiconductor Manufacturing	IEEE Transactions on Semiconductor Manufacturing	2019	134
38	Advanced Dicing Technology for Semiconductor Wafer—Stealth Dicing	IEEE Transactions on Semiconductor Manufacturing	2007	131
39	Analysis of Wafer Sojourn Time in Dual-Arm Cluster Tools With Residency Time Constraint and Activity Time Variation	IEEE Transactions on Semiconductor Manufacturing	2010	131
40	A plasticity-based model of material removal in chemical-mechanical polishing (CMP)	IEEE Transactions on Semiconductor Manufacturing	2001	129
41	Petri Net Modeling and Wafer Sojourn Time Analysis of Single-Arm Cluster Tools With Residency Time Constraints and Activity Time Variation	IEEE Transactions on Semiconductor Manufacturing	2012	129
42	Wafer Map Defect Detection and Recognition Using Joint Local and Nonlocal Linear Discriminant Analysis	IEEE Transactions on Semiconductor Manufacturing	2016	129
43	A new scheduling approach using combined dispatching criteria in wafer fabs	IEEE Transactions on Semiconductor Manufacturing	2003	127
44	Decision Tree Ensemble-Based Wafer Map Failure Pattern Recognition Based on Radon Transform-Based Features	IEEE Transactions on Semiconductor Manufacturing	2018	125
45	Specular spectroscopic scatterometry	IEEE Transactions on Semiconductor Manufacturing	2001	124
46	A Petri Net-Based Novel Scheduling Approach and Its Cycle Time Analysis for Dual-Arm Cluster Tools With Wafer Revisiting	IEEE Transactions on Semiconductor Manufacturing	2013	124
47	Multicluster Tools Scheduling: An Integrated Event Graph and Network Model Approach	IEEE Transactions on Semiconductor Manufacturing	2006	123
48	A queueing network model for semiconductor manufacturing	IEEE Transactions on Semiconductor Manufacturing	1996	121
49	Petri Net-Based Optimal One-Wafer Scheduling of Single-Arm Multi-Cluster Tools in Semiconductor Manufacturing	IEEE Transactions on Semiconductor Manufacturing	2013	121
50	An overview of level set methods for etching, deposition, and lithography development	IEEE Transactions on Semiconductor Manufacturing	1997	119

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