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Design of a 30 Nm Novel 3-D Quad Gate Stacked Nano-Sheets FinFET

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Abstract

Fin Field Effect Transistors (FinFETs) have appeared as a replacement for devices like Metal Oxide Semiconductor Field Effect Transistor (MOSFET) at low power operations. This paper presents a novel 3-D Quad gate FinFET device designed with vertically stacked Nano-sheets. This device is designed on COGENDA TCAD (Tanner Computer Aided Design) tool at 30 nm technology node. From the general model of tri-gate FinFET, the structure is modified with a new design approach. The approach includes addition of fourth gate to the basic FinFET tri-gate structure. Also, inclusion of three vertically stacked Nano-sheets as fins forms a new structure of Quad Gate vertically Stacked Nano-sheets FinFET (QG-SNS FinFET). The simulation results reveal that the designed device manifests steep Sub-threshold Slope (SS) of 26.7 mV/ decade, remarkably reduced OFF state current (IOFF) of the order of 9.85 × 10−14 A and comparable ON current (ION) of 1.0 × 10−5 A. The performance investigation of the device also includes cut off frequency (FT), threshold voltage (Vth), total gate capacitance (CGG) and transconductance (Gm). Hence the designed device is well suited for low power and high performance applications.

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References

  1. Gupta KA, Anvekar DK, Venkateswarlu V (2013) Modeling of Short Channel MOSFET devices and analysis of design aspects for power optimisation. Int J Model Optim 3(3):266–271

    Article  Google Scholar 

  2. Bakar ARA, Saad I (2016) Investigation on effect of tilt angle ion implantations for vertical double gate MOSFET. IEEE Reg Symp Micro Nanoelectron:100–103

  3. Kuhn KJ (2011) CMOS scaling for the 22nm node and beyond: Device physics and technology. Int Symp VLSI Technol Syst Appl Proc 2–3, https://doi.org/10.1109/VTSA.2011.5872206

  4. Rahul J, Srivastava A, Yadav S, Jha K (2012) Performance evaluation of junctionless vertical double gate MOSFET. Int Conf Device Circ Sys (ICDCS), IEEE 2012:440–442

  5. Mishra A, Jha K, Pattanaik M (2014) Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode. Microelectron J 45(11):1515–1521

    Article  Google Scholar 

  6. Skotnicki T, Hutchby JA, King T (2005) The end of CMOS scaling. IEEE Circuits Devices Mag 21(1):16–26

    Article  Google Scholar 

  7. Miao J, Zhang S, Cai L, Scherr M, Wang C (2015) Ultrashort Channel length black phosphorus field-effect transistors. ACS Nano 9(9):9236–9243

    Article  CAS  Google Scholar 

  8. Ferain I, Colinge CA, Colinge JP (2011) Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors. Nature 479(7373):310–316

    Article  CAS  Google Scholar 

  9. Kumar A, Pattanaik M, Srivastava P, Jha K (2020) Reduction of drain induced barrier lowering in DM-HD-NA GAAFET for RF applications. IET Circuits Devices Syst 14(3):270–275

    Article  Google Scholar 

  10. Burenkov A, Lorentz J (2003) Corner effect in double and triple gate FinFETs. Proc. European Solid State Device Research Conference. 135–138, https://doi.org/10.1109/ESSDERC.2003.1256829

  11. Burenkov A, Lorentz J (2003) On the role of corner effect in FinFETs. Proc. European Workshop on Ultimate Integration of Silicon (ULIS). 31–34, https://publica-stage.fraunhofer.de/handle/publica/343652

  12. Kranti A, Armstrong GA (2006) Performance assessment of nanoscale double and triple gate FinFETs. Semicond Sci Technol 21:409–421

    Article  CAS  Google Scholar 

  13. Nawaz M, Molzer W, Haibach P, Landgraf E, Roesner W, Staedele M, Luyken H, Gencer A (2006) Validation of 30 nm process simulation using 3D TCAD for FinFET devices. Semicond Sci Technol 21(8):1111–1120

    Article  CAS  Google Scholar 

  14. Granzner R et al (2002) A simulation study on three dimensional device design of wire-MOSFETs, Proc. European Workshop on Ultimate Integration of Silicon (ULIS). 1:95–98

  15. Doyle BS, Datta S, Doczy M, Hareland S, Jin B, Kavalieros J, Linton T, Murthy A, Chau R (2003) High performance fully depleted tri-gate CMOS transistors. IEEE Electron Device Lett 24(4):263–265

    Article  CAS  Google Scholar 

  16. Authetal C (2012) A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. Proc VLSI Technol Symp Dig Tech Papers, 131–132, https://doi.org/10.1109/VLSIT.2012.6242496

  17. Khakifirooz A et al (2012) Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS. Proc Symp VLSI Technol:117–118

  18. “Intel’s Revolutionary 22nm Transistor Technology, May (2011),“http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-details.presentation.pdf. Accessed 18/10/2021

  19. Loubet N, Hook T, Montanini P, Yeung CW, Kanakasabapathy S, Guillom M, Wang J (2017) Stacked Nano-Sheet gate-all-around transistor to enable scaling beyond FinFET. 2017 Symp VLSI Technol, https://doi.org/10.23919/VLSIT.2017.7998183

  20. Barraud S, Lapras V, Previtali B, Samson MP, Lacord J, Martinie S, Ernst T (2017) Performance and design considerations for gate-all-around stacked-Nano Wires FETs. IEEE IEDM, https://doi.org/10.1109/IEDM.2017.8268473

  21. Jain N, Raj B (2019) Thermal stability analysis and performance exploration of asymmetrical dual-k underlap spacer (ADKUS) SOI FinFET for security and privacy applications. Indian J Pure Appl Phys 57:352–360

    Google Scholar 

  22. Jain N, Raj B (2019) SOI FinFET for Computer Networks and Cyber Security Systems. Handbook of Computer Networks and Cyber Security: Principles and Paradigms, Springer. Chapter No. 12

  23. Khandelwal S, Raj B, Gupta RD (2015) FinFET based 6T SRAM Cell Design: Analysis of Performance Metric, Process Variation and Temperature Effect. J Comput Theor Nanosci 12:2500–2506

    Article  CAS  Google Scholar 

  24. Khandelwal S, Gupta V, Raj B, Gupta RD (2015) Process variability aware low leakage reliable Nano scale DG-FinFET SRAM cell design technique. J Nanoelectron Optoelectron 10(6):810–817

    Article  Google Scholar 

  25. Ruhil S, Khanna V, Dutta U, Shukla NK (2021) A study of emerging semi-conductor devices for memory applications. Int J Nano Dimens 12(3):186–120

    CAS  Google Scholar 

  26. Zhang Z, Jiang X, Wang R, Guo S, Wang Y, Huang R (2018) Extraction of process variation parameters in FinFET technology based on compact modeling and characterization. IEEE Trans Electron Devices 65(3):847–854

    Article  CAS  Google Scholar 

  27. International Technology Roadmap for Semiconductors (2003) https://www.semiconductors.org/resources/2003-international-technology-roadmap-for-semiconductorsitrs/. Accessed: 01/11/2021

  28. Dutta U, Soni MK, Pattanaik M (2018) Design and optimisation of GATE-all-around tunnel FET for low power applications. Int J Eng Technol 7(4):2263–2270

    Article  CAS  Google Scholar 

  29. Genius, 3-D Device Simulator (2019) Version 1.9.3–18, Reference Manual, Cogenda Pvt. Ltd., Singapore, https://www.cogenda.com/article/downloads. Accessed: 15/11/2021

  30. Abdi DB, Kumar MJ (2014) Controlling Ambipolar current in tunneling FET’s using overlapping gate-on drain. J Electron Devices Soc 2(6):187–190

    Article  Google Scholar 

  31. Amestoy PR, Duff IS, Koster J, L’Excellent J-Y (2001) A fully asynchronous multifrontal solver using distributed dynamic scheduling. SIAM J of Matrix Anal Appl 23:15–41

    Article  Google Scholar 

  32. Amestoy PR, Guermouche A, Excellent J-YL, Pralet S (2006) Hybrid scheduling for the parallel solution of linear systems. Parallel Comput Elsevier 32:136–156

    Article  Google Scholar 

  33. Palankovski V, Kaiblinger-Grujin G, Kosina H, Selberherr S (1998) A dopant-dependent band gap narrowing model application for bipolar device simulation. Int. Conf. Simul. Semicond. Process Devices, https://doi.org/10.1007/978-3-7091-6827-1_29

  34. Vakkalakula BS, Vadthiya N (2021) Design and temperature assessment of junctionless nanosheet FET for nanoscale applications. Silicon, https://doi.org/10.1007/s12633-021-01145-w

  35. International Technology Roadmap for Semiconductors (2018) https://en.wikipedia.org/wiki. Accessed 30/10/2021

  36. Ye P, Ernst T, Khare MV (2019) The last silicon transistor: Nanosheet devices could be the final evolutionary step for Moore’s law. IEEE Spectr 56:30–35

    Article  Google Scholar 

  37. Dash TP, Dey S, Mohapatra E, Das S, Jena J (2019) Vertically stacked silicon Nanosheet field effect transistors at 3nm technology nodes. DevIC:99–103

  38. Rassekh A, Fathipour MA (2020) Single-gate SOI nanosheet junctionless transistor at 10-nm gate length: design guidelines and comparison with the conventional SOI FinFET. J Comput Electron 19:631–639, https://doi.org/10.23919/VLSIT.2017.7998183

    Article  CAS  Google Scholar 

  39. Boucart K, Ionescu AM (2007) Double-Gate Tunnel FET with High-k Gate Dielectric. IEEE Trans Electron Devices 54(7):1725–1733

    Article  CAS  Google Scholar 

  40. Ortiz-Conde, A.; Garcìa Sánchez, F. J.; Liou, J.J; Cerdeira, A.; Estrada, M.; and Yue, Y. a review of recent MOSFET threshold voltage extraction methods, microelectron. Reliab. 2002, 42 (4–5), 583–596

  41. Dutta U, Soni MK, Pattanaik M (2018) Simulation study of hetero dielectric tri material gate tunnel FET based common source amplifier circuit. Int J Electron Commun 9:2263–2270

    Google Scholar 

  42. Prasad M, Mahadevaswamy UB (2021) Density gradient study on Junctionless stack Nano-sheet with stack gate oxide for low power application. IETE J Res, https://doi.org/10.1080/03772063.2020.1869594

  43. Wu S-Y et al (2013) A 16 nm FinFET CMOS technology for mobile SoC and computing applications. IEDM Tech Dig pp. 9.1.1–9.1.4, https://doi.org/10.1109/IEDM.2013.6724591

  44. Lin H-C, Chou Chung C-C; Tsen CJ, Huang B-W, Liu CWRF (2021) Performance of Stacked Si Nano sheet nFETs, IEEE Trans Electron Devices

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Acknowledgments

We thank Manav Rachna International Institute of Research and Studies, Faridabad for the lab facilities to carry out this work.

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Authors and Affiliations

  1. Department of Electrical, Electronics and Communication Engineering, The NorthCap University, Gurgaon, India

    Shaifali Ruhil & Vandana Khanna

  2. Department of Electronics and Communication Engineering, Manav Rachna International Institute of Research and Studies, Faridabad, India

    Umesh Dutta

  3. Department of Electrical Engineering, King Khalid University Abha, Abha, Kingdom of Saudi Arabia

    Neeraj Kumar Shukla

Authors
  1. Shaifali Ruhil
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  2. Umesh Dutta
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  3. Vandana Khanna
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  4. Neeraj Kumar Shukla
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Contributions

Design and simulation of the device were performed by Shaifali Ruhil and Dr. Umesh Dutta. Data collection, material preparation and analysis were done by Shaifali Ruhil, Dr. Vandana Khanna and Dr. Umesh Dutta. The initial manuscript draft was written by Shaifali Ruhil. The manuscript was edited and reviewed by Dr. Vandana Khanna, Shaifali Ruhil, Dr. Umesh Dutta and Dr. Neeraj Kumar Shukla.

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Correspondence to Shaifali Ruhil.

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All procedures performed in this study follow the ethical standards of the institutional and research committee.

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Ruhil, S., Dutta, U., Khanna, V. et al. Design of a 30 Nm Novel 3-D Quad Gate Stacked Nano-Sheets FinFET. Silicon 14, 11859–11868 (2022). https://doi.org/10.1007/s12633-022-01911-4

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