Abstract
Our silicon industries are giving indicator that they are having shortage of expertise in IC design especially from local graduates. On top of that the employed graduates are also lacking of skills. IC design involves with wide topics due to wide application. Specialization is normally related to application such as RF design, memory design, analog design, and digital design. Expertise may end up with specializing in one or two applications only due to long effort to capture the whole skill and knowledge. It is known that the process to build up expertise in this field is hard and challenging. The degree structure needs to equip with high-end software, experience staff, and fund for fabrication. Most programs aim is to produce high level of graduate with good competitive skills that would help the silicon industries to employ them without retrain issue. Hence, in this article, a compilation of teaching process is shared which involves a highly skill mentor who is guiding the trainee on the design process. The sample results concluded that teaching advanced technology in IC design requires sophisticated facilities as well as experienced trainers.
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References
Amir M, Zazalinda I (2020) Design and test on-chip power-on-reset (POR) function in battery switchover IC. AIP Conf Proc 2291:020011. https://doi.org/10.1063/5.0023517
Abas MA, Rusli MAM, Sakrani S, Aizudin NIZ, Syari AA (2012) Graduate enhancement programme for building up IC layout technologies. J Eng Technol 2:66–71
Intan N, Abas MA, Sakrani S (2010) Design an integrated microprocessor supervisory chip for monitoring power failure. In: 34th IEEE/CPMT international electronic manufacturing technology symposium (IEMT), pp 1–6. https://doi.org/10.1109/IEMT.2010.5746694
Intan N, Abas MA, Sakrani S, Afham M (2009) Grooming IC designer through apprenticeship programme. In: 2009 IEEE symposium on industrial electronics & applications, ISIEA 2009, pp 542–547
Etienne S, Sonia DB (2007) Advanced CMOS cell design. Tata McGraw-Hill, New Delhi
Dan C (2000) CMOS IC layout concepts, methodologies, and tools. Newnes, Butter-worth Heinemann
Allan GA, Walton AJ, Holwill RJ (1992) A yield improvement technique for IC layout using local design rules. IEEE TCAD 11(11):1355–1362
Ming DK, Chung YW, Tain SW (1997) Area-efficient layout design for CMOS output transistors. IEEE Trans Electron Devices 44(4):635–645
Satoru K, Yasunori S, Hiroaki T, Atsuo H, Isao O (1994) Transistor size optimization in layout design rule migration. IEEE Cust Integr Circuits, pp 542–544
Steven T (2010) Gridless IC layout and method and apparatus for generating such a layout. http://en.wikipedia.org/wiki. U.S. Patent 6 957 411
Acknowledgements
The author would like to applause to our highly experience mentor S. Sakrani from ICmic Academy. He has shared his vast experience in IC design which makes the flow of the project beneficial to the trainee and UniKL. His couching, skill, and knowledge have been captured and compiled as a reference for future study in fostering more graduate specializing in IC design.
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Abas, M.A., Zazalinda, N.I. (2022). Experiencing Layout Design Techniques from Highly Skilled IC Design Engineers. In: Ismail, A., Dahalan, W.M., Öchsner, A. (eds) Advanced Materials and Engineering Technologies. Advanced Structured Materials, vol 162. Springer, Cham. https://doi.org/10.1007/978-3-030-92964-0_28
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DOI: https://doi.org/10.1007/978-3-030-92964-0_28
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