Abstract
Modern non-volatile memory storage devices operate significantly faster than traditional rotating disk media. Disk paging, though never intended for use as an active memory displacement scheme, may be viable as a cost-efficient cache between main memory and sufficiently fast secondary storage. However, existing benchmarks are not designed to accurately measure the microsecond-level latencies at which next-generation storage devices are expected to perform. Furthermore, full exploitation of disk paging to fast storage media will require considerations in the design of operating system paging algorithms. This paper presents pmbench – a multiplatform synthetic micro-benchmark that profiles system paging characteristics by accurately measuring the latency of paging-related memory access operations. Also presented are sample pmbench results on Linux and Windows using a consumer NAND-based SSD and a prototype low-latency SSD as swap devices. These results implicate operating system-induced software overhead as a major bottleneck for system paging, which intensifies as SSD latencies decrease.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
For example, a latency measurement of 9,231 ns will increment the 3rd counter in the 8,192 (213)–16,384(214) ns bucket.
- 2.
Exact command was: pmbench -m 8192 -s 8192 -j 2 -r 50 -d 0 -o -1 -p uniform -t rdtscp -c -i 300
References
Flexible I/O tester (FIO). https://github.com/axboe/fio. Accessed 28 Oct 2016.
Iometer. http://www.iometer.org/. Accessed 28 Oct 2016.
Lmbench Source. https://sourceforge.net/projects/lmbench/. Accessed 28 Oct 2016.
PMBench. https://bitbucket.org/jisooy/pmbench. Accessed 28 Oct 2016.
Badam, A., & Pai, V. S. (2011). SSDAlloc: Hybrid SSD/RAM memory management made easy. In Proceedings of the 9th USENIX Symposium on Networked Systems Design and Implementation (NSDI), Boston, MA.
Bovet, D. P., & Cesati, M. (2005). Understanding the Linux kernel. Sevastopol: O’Reilly.
Caulfield, A. M., Mollov, T. I., Eisner, L. A., De, A., Coburn, J., & Swanson, S. (2012). Providing safe, user space access to fast, solid state disks. In Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), London, UK.
Creeger, E. Windows 10: Memory compression. https://riverar.github.io/insiderhubcontent/memory_compression.html. Accessed 28 Oct 2016.
Dulloor, S. R., Kumar, S., Keshavamurthy, A., Lantz, P., Reddy, D., Sankaran, R., & Jackson, J. (2014). System software for persistent memory. In Proceedings of the 9th European Conference on Computer Systems (EuroSys’14), Amsterdam.
Grupp, L. M., Davis, J. D., & Swanson, S. (2012). The bleak future of NAND Flash memory. In Proceedings of the 2012 USENIX/ACM Conference on File and Storage Technologies (FAST), San Jose, CA.
Lee, B. C., Ipek, E., Mutlu, O., & Burger, D. (2009). Architecting phase change memory as a scalable DRAM alternative. In Proceedings of the 36th International Symposium on Computer Architecture (ISCA’09), Austin, TX.
McVoy, L., & Staelin, C. (1996). Lmbench: Portable tools for performance analysis. In Proceedings of the USENIX 1996 Annual Technical Conference, San Diego, CA.
Mishra, A. K., Dong, X., Sun, G., Xie, Y., Vijaykrishnan, N., & Das, C. R. (2011). Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. In Proceedings of the 38th International Symposium on Computer Architecture (ISCA’11), San Jose, CA.
Park, S., Kelly, T., & Shen, K. (2013). Failure-atomic msync(): A simple and efficient mechanism for preserving the integrity of durable data. In Proceedings of the 8th ACM European Conference on Computer Systems (EuroSys’13), Prague, Czech Republic.
Satyanarayanan, M., Mashburn, H. H., Kumar, P., Steere, D. C., & Kistler, J. J. (1993). Lightweight recoverable virtual memory. In Proceedings of the 14th ACM Symposium on Operating System Principles (SOSP’93), Asheville, NC.
Kau, D., et al. (2009). A stackable cross point phase change memory. In Proceedings of the 2009 I.E. International Electron Devices Meeting (IEDM), Baltimore, MD (pp. 1–4).
Im, J.-W., et al. (2015). A 128Gb 3b/cell V-NAND Flash memory with 1gb/s I/O rate. In Proceedings of the 2015 International Solid-State Circuits Conference (ISSCC), San Francisco, CA.
Chun, K. C., et al. (2013). A scaling roadmap and performance evaluation of in-plane and perpendicular MTJ based STT-MRAMs for high-density cache memory. IEEE Journal of Solid-State Circuits, 48(2), 598–610.
Fackenthal, R., et al. (2014). A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology. In Proceedings of the 2014 International Solid-State Circuits Conference (ISSCC), San Francisco, CA.
Choi, Y., et al. (2012). A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth. In Proceedings of the 2012 International Solid-State Circuits Conference (ISSCC), San Francisco, CA.
Wilson, P. R., Kaplan, S. F., & Smaragdakis, Y. (1999). The case for compressed caching in virtual memory systems. In Proceedings of the USENIX Annual Technical Conference, Monterey, CA.
Yang, J., Minturn, D., & Hady, F. (2012). When poll is better than interrupt. In Proceedings of the 2012 USENIX/ACM File and Storage Technology (FAST), Santa Clara, CA.
Acknowledgements
We thank the anonymous reviewers for their valuable feedback. This work was supported by an award from Intel Corporation.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer International Publishing AG
About this paper
Cite this paper
Yang, J., Seymour, J. (2018). Pmbench: A Micro-Benchmark for Profiling Paging Performance on a System with Low-Latency SSDs. In: Latifi, S. (eds) Information Technology - New Generations. Advances in Intelligent Systems and Computing, vol 558. Springer, Cham. https://doi.org/10.1007/978-3-319-54978-1_79
Download citation
DOI: https://doi.org/10.1007/978-3-319-54978-1_79
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-54977-4
Online ISBN: 978-3-319-54978-1
eBook Packages: EngineeringEngineering (R0)