3.1(top 20%)
impact factor
5.6K(top 5%)
papers
120.6K(top 5%)
citations
119(top 5%)
h-index
3.2(top 20%)
extended IF
6.7K
all documents
130.0K
doc citations
184(top 5%)
g-index
Top Articles
| # | Title | Journal | Year | Citations |
|---|---|---|---|---|
| 1 | A survey of design techniques for system-level dynamic power management | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2000 | 974 |
| 2 | HotSpot: a compact thermal modeling methodology for early-stage VLSI design | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2006 | 873 |
| 3 | Bus-invert coding for low-power I/O | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1995 | 815 |
| 4 | Power analysis of embedded software: a first step towards software power minimization | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1994 | 801 |
| 5 | Vibration-to-electric energy conversion | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2001 | 737 |
| 6 | Extracting secret keys from integrated circuits | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2005 | 706 |
| 7 | Multilevel hypergraph partitioning: applications in VLSI domain | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1999 | 554 |
| 8 | A survey of power estimation techniques in VLSI circuits | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1994 | 527 |
| 9 | Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2014 | 478 |
| 10 | Low-power digital systems based on adiabatic-switching principles | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1994 | 477 |
| 11 | High-throughput LDPC decoders | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2003 | 452 |
| 12 | Performance analysis of low-power 1-bit CMOS full adder cells | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2002 | 376 |
| 13 | "It's a small world after all": NoC performance optimization via long-range link insertion | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2006 | 353 |
| 14 | Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2014 | 351 |
| 15 | Effects of inductance on the propagation delay and repeater insertion in VLSI circuits | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2000 | 344 |
| 16 | High-speed VLSI architectures for the AES algorithm | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2004 | 344 |
| 17 | Predictive system shutdown and other architectural techniques for energy efficient programmable computation | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1996 | 338 |
| 18 | Fixed-outline floorplanning: enabling hierarchical design | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2003 | 333 |
| 19 | 3-D Topologies for Networks-on-Chip | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2007 | 324 |
| 20 | Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2006 | 322 |
| 21 | Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2017 | 317 |
| 22 | A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2019 | 317 |
| 23 | Architectural power analysis: The dual bit type method | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1995 | 313 |
| 24 | A Monte Carlo approach for power estimation | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1993 | 308 |
| 25 | A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2005 | 303 |
| 26 | VLSI architectures for discrete wavelet transforms | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1993 | 297 |
| 27 | The effect of LUT and cluster size on deep-submicron FPGA performance and density | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2004 | 295 |
| 28 | Programmable active memories: reconfigurable systems come of age | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1996 | 275 |
| 29 | Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2010 | 269 |
| 30 | Precomputation-based sequential logic optimization for low power | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1994 | 268 |
| 31 | Low-Power and Area-Efficient Carry Select Adder | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2012 | 267 |
| 32 | Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2002 | 266 |
| 33 | Design of Power and Area Efficient Approximate Multipliers | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2017 | 266 |
| 34 | CMOS Full-Adders for Energy-Efficient Arithmetic Applications | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2011 | 264 |
| 35 | High-speed architectures for Reed-Solomon decoders | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2001 | 257 |
| 36 | Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2017 | 253 |
| 37 | Design and optimization of dual-threshold circuits for low-voltage low-power applications | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1999 | 251 |
| 38 | Computing in Memory With Spin-Transfer Torque Magnetic RAM | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2018 | 251 |
| 39 | Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2018 | 247 |
| 40 | The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2010 | 244 |
| 41 | Robust subthreshold logic for ultra-low power operation | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2001 | 242 |
| 42 | A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2012 | 240 |
| 43 | An analytical model for predicting the remaining battery capacity of lithium-ion batteries | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2006 | 239 |
| 44 | Low-swing on-chip signaling techniques: effectiveness and robustness | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2000 | 238 |
| 45 | Soft digital signal processing | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2001 | 238 |
| 46 | Scheduling tests for VLSI systems under power constraints | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1997 | 234 |
| 47 | Energy minimization using multiple supply voltages | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1997 | 233 |
| 48 | Characterization of a Novel Nine-Transistor SRAM Cell | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2008 | 223 |
| 49 | Embedded power supply for low-power DSP | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1997 | 222 |
| 50 | Computation on Stochastic Bit Streams Digital Image Processing Case Studies | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2014 | 221 |