2.9(top 20%)
impact factor
7.6K(top 5%)
papers
187.1K(top 2%)
citations
149(top 2%)
h-index
2.9(top 20%)
extended IF
9.5K
all documents
221.4K
doc citations
237(top 5%)
g-index
Top Articles
| # | Title | Journal | Year | Citations |
|---|---|---|---|---|
| 1 | Asymptotic waveform evaluation for timing analysis | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1990 | 1,576 |
| 2 | TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2015 | 1,351 |
| 3 | PRIMA: passive reduced-order interconnect macromodeling algorithm | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1998 | 1,174 |
| 4 | Efficient linear circuit analysis by Pade approximation via the Lanczos process | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1995 | 1,120 |
| 5 | MIS: A Multiple-Level Logic Optimization System | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1987 | 965 |
| 6 | New spectral methods for ratio cut partitioning and clustering | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1992 | 963 |
| 7 | Force-directed scheduling for the behavioral synthesis of ASICs | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1989 | 909 |
| 8 | NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2012 | 905 |
| 9 | FastCap: a multipole accelerated 3-D capacitance extraction program | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1991 | 777 |
| 10 | Measuring the Gap Between FPGAs and ASICs | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2007 | 768 |
| 11 | System-level design: orthogonalization of concerns and platform-based design | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2000 | 724 |
| 12 | Low-Power Digital Signal Processing Using Approximate Adders | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2013 | 715 |
| 13 | A physically based mobility model for numerical simulation of nonplanar devices | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1988 | 701 |
| 14 | Signal Delay in RC Tree Networks | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1983 | 695 |
| 15 | High-Level Synthesis for FPGAs: From Prototyping to Deployment | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2011 | 680 |
| 16 | The Waveform Relaxation Method for Time-Domain Analysis of Large Scale Integrated Circuits | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1982 | 674 |
| 17 | VLSI module placement based on rectangle-packing by the sequence-pair | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1996 | 636 |
| 18 | A precorrected-FFT method for electrostatic analysis of complicated 3-D structures | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1997 | 614 |
| 19 | Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2009 | 594 |
| 20 | Test pattern generation using Boolean satisfiability | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1992 | 566 |
| 21 | Synthesis of quantum-logic circuits | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2006 | 541 |
| 22 | NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2018 | 536 |
| 23 | FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1994 | 525 |
| 24 | A framework for comparing models of computation | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1998 | 523 |
| 25 | Energy- and performance-aware mapping for regular NoC architectures | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2005 | 516 |
| 26 | Efficient Algorithms for Channel Routing | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1982 | 482 |
| 27 | Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2018 | 481 |
| 28 | A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2003 | 470 |
| 29 | SOCRATES: a highly efficient automatic test pattern generation system | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1988 | 465 |
| 30 | Embedded Deterministic Test | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2004 | 462 |
| 31 | Automated Synthesis of Data Paths in Digital Systems | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1986 | 447 |
| 32 | Optimal design of a CMOS op-amp via geometric programming | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2001 | 440 |
| 33 | A Survey and Evaluation of FPGA High-Level Synthesis Tools | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2016 | 439 |
| 34 | Synthesis of reversible logic circuits | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2003 | 438 |
| 35 | On Delay Fault Testing in Logic Circuits | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1987 | 432 |
| 36 | GORDIAN: VLSI placement by quadratic programming and slicing optimization | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1991 | 424 |
| 37 | HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2009 | 422 |
| 38 | A Meet-in-the-Middle Algorithm for Fast Synthesis of Depth-Optimal Quantum Circuits | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2013 | 418 |
| 39 | DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained IoT Edge Clusters | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2018 | 409 |
| 40 | Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modeling | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1990 | 408 |
| 41 | A Procedure for Placement of Standard-Cell VLSI Circuits | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1985 | 406 |
| 42 | Symbolic model checking for sequential circuit verification | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1994 | 388 |
| 43 | Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2005 | 385 |
| 44 | CMOS Circuit Speed and Buffer Optimization | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1987 | 378 |
| 45 | Optimizing power using transformations | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1995 | 365 |
| 46 | Simulation of Nonlinear Circuits in the Frequency Domain | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1986 | 364 |
| 47 | OASYS: a framework for analog circuit synthesis | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1989 | 361 |
| 48 | Multiprocessor System-on-Chip (MPSoC) Technology | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2008 | 355 |
| 49 | Policy optimization for dynamic power management | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1999 | 354 |
| 50 | A formal approach to the scheduling problem in high level synthesis | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1991 | 350 |