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365 peer-reviewed articles • 15,899 peer-reviewed citations • Sorted by year • Download PDF (PDF by citations)
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1Utilizing Symmetric BSIM-SOI SPICE Model for Dynamically Depleted RF SOI T/R Switches and Logic Circuits
IEEE Journal of the Electron Devices Society, 2025, 13, 800-807
1.86Citations (PDF)
2Ultra-Thin Body, Short Channel Silicon Transistors Down to 3-nm Si Channel
IEEE Electron Device Letters, 2025, 46, 258-261
3.42Citations (PDF)
3Boltzmann-Statistics-Aware Non-Quasi-Static-Charge Model for IC Simulations
IEEE Transactions on Electron Devices, 2025, 72, 357-363
2.70Citations (PDF)
4Impact Ionization in LDMOS Transistors: Improved Compact Model and Asymmetry Under Forward and Reverse Modes of Operation
IEEE Journal of the Electron Devices Society, 2025, 13, 863-869
1.81Citations (PDF)
5A multi-stage neural network I-V and C-V BSIM-CMG model global parameter extractor for advanced GAAFET technologies
Solid-State Electronics, 2025, 226, 109081
1.15Citations (PDF)
6Demonstration of High Transconductance Gate-All-Around Transistors Using Negative Capacitance ‘Super High-K’ Gate Stack
IEEE Electron Device Letters, 2025, 46, 533-536
3.43Citations (PDF)
7Application of explainable AI on deep learning-based gate length scalable IV parameter extractor for BSIM-IMG
Solid-State Electronics, 2025, 229, 109154
1.10Citations (PDF)
8A Compact Model for Perpendicular STT-MRAM Incorporating Free and Pinned Layer Thickness Dependence, Accurate Bias Dependence, and Real-Time 3-D Switching Dynamics
IEEE Transactions on Electron Devices, 2025, 72, 4123-4130
2.71Citations (PDF)
9Comprehensive High-Voltage Parameter Extraction Strategy for BSIM-BULK HV Model
IEEE Transactions on Electron Devices, 2024, 71, 70-76
2.77Citations (PDF)
10A Compact Model of Perpendicular Spin-Transfer-Torque Magnetic Tunnel Junction
IEEE Transactions on Electron Devices, 2024, 71, 57-61
2.79Citations (PDF)
11Boost in Carrier Velocity Due to Electrostatic Effects of Negative Capacitance Gate Stack
IEEE Electron Device Letters, 2024, 45, 460-463
3.41Citations (PDF)
12Symmetric BSIM-SOI—Part II: A Compact Model for Partially Depleted SOI MOSFETs
IEEE Transactions on Electron Devices, 2024, 71, 2293-2300
2.78Citations (PDF)
13Symmetric BSIM-SOI—Part I: A Compact Model for Dynamically Depleted SOI MOSFETs
IEEE Transactions on Electron Devices, 2024, 71, 2284-2292
2.718Citations (PDF)
14A single neural network global I-V and C-V parameter extractor for BSIM-CMG compact model
Solid-State Electronics, 2024, 216, 108898
1.121Citations (PDF)
15Compact Modeling of Impact Ionization and Conductivity Modulation in LDMOS Transistors
IEEE Transactions on Electron Devices, 2024, 71, 4240-4246
2.77Citations (PDF)
16A Novel Neural Network-Based Transistor Compact Model Including Self-Heating
IEEE Electron Device Letters, 2024, 45, 1512-1515
3.412Citations (PDF)
17An All-Region BSIM Thin-Film Transistor Model for Display and BEOL 3-D Integration Applications
IEEE Transactions on Electron Devices, 2024, 71, 4701-4709
2.79Citations (PDF)
18Extending Standard BSIM-BULK Model to Cryogenic Temperatures
IEEE Transactions on Electron Devices, 2024, 71, 4510-4516
2.712Citations (PDF)
19Non-Quasi-Static Modeling of Neural Network-Based Transistor Compact Model for Fast Transient, AC, and RF Simulations
IEEE Electron Device Letters, 2024, 45, 1277-1280
3.46Citations (PDF)
20A versatile compact model of resistive random-access memory (RRAM)
Solid-State Electronics, 2024, 220, 108989
1.15Citations (PDF)
21Physical Insights and Accurate Modeling of Transconductance in Body-Contacted Dynamically Depleted SOI MOSFETs
IEEE Transactions on Electron Devices, 2024, 71, 6506-6513
2.79Citations (PDF)
22Robust Compact Model of High-Voltage MOSFET’s Drift Region
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023, 42, 337-340
1.718Citations (PDF)
23Compact Modeling of Impact Ionization in High-Voltage Devices
IEEE Transactions on Electron Devices, 2023, 70, 2389-2394
2.711Citations (PDF)
24Neural Network-Based BSIM Transistor Model Framework: Currents, Charges, Variability, and Circuit Simulation
IEEE Transactions on Electron Devices, 2023, 70, 2157-2160
2.754Citations (PDF)
25Single-Crystal Germanium by Elevated-Laser-Liquid-Phase-Epitaxy (ELLPE) Technique for Monolithic 3D ICs
IEEE Electron Device Letters, 2023, 44, 1036-1039
3.44Citations (PDF)
26A Comprehensive RF Characterization and Modeling Methodology for the 5nm Technology Node FinFETs
IEEE Journal of the Electron Devices Society, 2023, 11, 444-455
1.87Citations (PDF)
27Deep learning-based I-V Global Parameter Extraction for BSIM-CMG
Solid-State Electronics, 2023, 209, 108766
1.126Citations (PDF)
28Conformal bilayer h-AlN epitaxy on WS2 by ALD with ultralow leakage current
Applied Physics Letters, 2023, 123,
3.09Citations (PDF)
29A Compact Model of Antiferroelectric Capacitor
IEEE Electron Device Letters, 2022, 43, 316-318
3.47Citations (PDF)
30A Compact Model of Metal–Ferroelectric-Insulator–Semiconductor Tunnel Junction
IEEE Transactions on Electron Devices, 2022, 69, 414-418
2.714Citations (PDF)
31Enhancement of Ferroelectricity in 5 nm Metal-Ferroelectric-Insulator Technologies by Using a Strained TiN Electrode
Nanomaterials, 2022, 12, 468
4.02Citations (PDF)
32Engineering Hf0.5Zr0.5O2 Ferroelectric/Anti- Ferroelectric Phases With Oxygen Vacancy and Interface Energy Achieving High Remanent Polarization and Dielectric Constants
IEEE Electron Device Letters, 2022, 43, 553-556
3.464Citations (PDF)
33Fast Read-After-Write and Depolarization Fields in High Endurance n-Type Ferroelectric FETs
IEEE Electron Device Letters, 2022, 43, 717-720
3.460Citations (PDF)
34Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors
Nature, 2022, 604, 65-71
37.9359Citations (PDF)
35Deep-Learning-Assisted Physics-Driven MOSFET Current-Voltage Modeling
IEEE Electron Device Letters, 2022, 43, 974-977
3.497Citations (PDF)
36van der Waals epitaxy of 2D h-AlN on TMDs by atomic layer deposition at 250 °C
Applied Physics Letters, 2022, 120,
3.025Citations (PDF)
37A Compact Model of Nanoscale Ferroelectric Capacitor
IEEE Transactions on Electron Devices, 2022, 69, 4761-4764
2.75Citations (PDF)
38A Compact Model of Ferroelectric Field-Effect Transistor
IEEE Electron Device Letters, 2022, 43, 1363-1366
3.434Citations (PDF)
39Deep Learning-Based BSIM-CMG Parameter Extraction for 10-nm FinFET
IEEE Transactions on Electron Devices, 2022, 69, 4765-4768
2.770Citations (PDF)
40Critical Importance of Nonuniform Polarization and Fringe Field Effects for Scaled Ferroelectric FinFET Memory
IEEE Transactions on Electron Devices, 2022, 69, 4900-4908
2.78Citations (PDF)
41Neural Network-Based and Modeling With High Accuracy and Potential Model Speed
IEEE Transactions on Electron Devices, 2022, 69, 6476-6479
2.749Citations (PDF)
42Write Disturb-Free Ferroelectric FETs With Non-Accumulative Switching Dynamics
IEEE Electron Device Letters, 2022, 43, 2097-2100
3.421Citations (PDF)
43Electric Field-Induced Permittivity Enhancement in Negative-Capacitance FET
IEEE Transactions on Electron Devices, 2021, 68, 1346-1351
2.714Citations (PDF)
44Energy Storage and Reuse in Negative Capacitance
IEEE Transactions on Electron Devices, 2021, 68, 1861-1865
2.72Citations (PDF)
45Negative capacitance enables GAA scaling VDD to 0.5 V
Solid-State Electronics, 2021, 181-182, 108010
1.112Citations (PDF)
46Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures
IEEE Transactions on Electron Devices, 2021, 68, 4223-4230
2.7103Citations (PDF)
47S-Curve Engineering for ON-State Performance Using Anti-Ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET
IEEE Transactions on Electron Devices, 2021, 68, 4787-4792
2.76Citations (PDF)
48Single-Crystal Islands (SCI) for Monolithic 3-D and Back-End-of-Line FinFET Circuits
IEEE Transactions on Electron Devices, 2021, 68, 5257-5262
2.78Citations (PDF)
49A Compact Model of Polycrystalline Ferroelectric Capacitor
IEEE Transactions on Electron Devices, 2021, 68, 5311-5314
2.734Citations (PDF)
50Ferroelectric HfO2 Memory Transistors With High-κ Interfacial Layer and Write Endurance Exceeding 1010 Cycles
IEEE Electron Device Letters, 2021, 42, 994-997
3.4202Citations (PDF)
51Near Threshold Capacitance Matching in a Negative Capacitance FET With 1 nm Effective Oxide Thickness Gate Stack
IEEE Electron Device Letters, 2020, 41, 179-182
3.436Citations (PDF)
52BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs
IEEE Transactions on Electron Devices, 2020, 67, 730-737
2.767Citations (PDF)
53Experimental Demonstration of a Ferroelectric HfO2-Based Content Addressable Memory Cell
IEEE Electron Device Letters, 2020, 41, 240-243
3.461Citations (PDF)
54Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors
IEEE Electron Device Letters, 2020, 41, 1637-1640
3.458Citations (PDF)
55Modeling of Current Mismatch and 1/f Noise for Halo-Implanted Drain-Extended MOSFETs
IEEE Transactions on Electron Devices, 2020, 67, 4794-4801
2.75Citations (PDF)
56Design Optimization Techniques in Nanosheet Transistor for RF Applications
IEEE Transactions on Electron Devices, 2020, 67, 4515-4520
2.752Citations (PDF)
57Analysis and Modeling of Polarization Gradient Effect on Negative Capacitance FET
IEEE Transactions on Electron Devices, 2020, 67, 4521-4525
2.717Citations (PDF)
58Gate-All-Around FET Design Rule for Suppression of Excess Non-Linearity
IEEE Electron Device Letters, 2020, 41, 1750-1753
3.49Citations (PDF)
59Improved TDDB Reliability and Interface States in 5-nm Hf0.5Zr0.5O2 Ferroelectric Technologies Using NH3 Plasma and Microwave Annealing
IEEE Transactions on Electron Devices, 2020, 67, 1581-1585
2.747Citations (PDF)
60A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET
IEEE Journal of the Electron Devices Society, 2020, 8, 171-175
1.829Citations (PDF)
61Compact Model for Geometry Dependent Mobility in Nanosheet FETs
IEEE Electron Device Letters, 2020, 41, 313-316
3.436Citations (PDF)
62Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)
IEEE Transactions on Electron Devices, 2020, 67, 2593-2599
2.777Citations (PDF)
63A Density Metric for Semiconductor Technology [Point of View]
Proceedings of the IEEE, 2020, 108, 478-482
9.647Citations (PDF)
64Enhanced ferroelectricity in ultrathin films grown directly on silicon
Nature, 2020, 580, 478-482
37.9868Citations (PDF)
65BSIM-CMG Compact Model for IC CAD: from FinFET to Gate-All-Around FET Technology
Journal of Microelectronic Manufacturing, 2020, 3, 1-8
0.23Citations (PDF)
66Accurate and Computationally Efficient Modeling of Nonquasi Static Effects in MOSFETs for Millimeter-Wave Applications
IEEE Transactions on Electron Devices, 2019, 66, 44-51
2.718Citations (PDF)
67Anomalously Beneficial Gate-Length Scaling Trend of Negative Capacitance Transistors
IEEE Electron Device Letters, 2019, 40, 1860-1863
3.423Citations (PDF)
68Challenges to Partial Switching of Hf0.8Zr0.2O2 Gated Ferroelectric FET for Multilevel/Analog or Low-Voltage Memory Operation
IEEE Electron Device Letters, 2019, 40, 1423-1426
3.435Citations (PDF)
69Effects of Annealing on Ferroelectric Hafnium–Zirconium–Oxide-Based Transistor Technology
IEEE Electron Device Letters, 2019, 40, 467-470
3.440Citations (PDF)
70Improved Modeling of Bulk Charge Effect for BSIM-BULK Model
IEEE Transactions on Electron Devices, 2019, 66, 2850-2853
2.710Citations (PDF)
71Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology Node
IEEE Electron Device Letters, 2019, 40, 985-988
3.443Citations (PDF)
72Spacer Engineering in Negative Capacitance FinFETs
IEEE Electron Device Letters, 2019, 40, 1009-1012
3.445Citations (PDF)
73Negative Capacitance FET With 1.8-nm-Thick Zr-Doped HfO2 Oxide
IEEE Electron Device Letters, 2019, 40, 993-996
3.4143Citations (PDF)
74Optimization of NCFET by Matching Dielectric and Ferroelectric Nonuniformly Along the Channel
IEEE Electron Device Letters, 2019, 40, 822-825
3.421Citations (PDF)
75Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits
IEEE Transactions on Electron Devices, 2019, 66, 2004-2009
2.738Citations (PDF)
76Analysis and Modeling of Inner Fringing Field Effect on Negative Capacitance FinFETs
IEEE Transactions on Electron Devices, 2019, 66, 2023-2027
2.742Citations (PDF)
77Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors
IEEE Electron Device Letters, 2019, 40, 463-466
3.489Citations (PDF)
78Spatially resolved steady-state negative capacitance
Nature, 2019, 565, 468-471
37.9383Citations (PDF)
79Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition
IEEE Transactions on Electron Devices, 2018, 65, 1094-1100
2.724Citations (PDF)
80Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ Sensitivity in Presence of Parasitic Capacitance
IEEE Transactions on Electron Devices, 2018, 65, 1211-1216
2.733Citations (PDF)
81Engineering Negative Differential Resistance in NCFETs for Analog Applications
IEEE Transactions on Electron Devices, 2018, 65, 2033-2039
2.7101Citations (PDF)
82Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors
IEEE Electron Device Letters, 2018, 39, 300-303
3.4147Citations (PDF)
83A Nitrided Interfacial Oxide for Interface State Improvement in Hafnium Zirconium Oxide-Based Ferroelectric Transistor Technology
IEEE Electron Device Letters, 2018, 39, 95-98
3.438Citations (PDF)
84Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor
IEEE Transactions on Electron Devices, 2018, 65, 4652-4658
2.735Citations (PDF)
85Modeling of Induced Gate Thermal Noise Including Back-Bias Effect in FDSOI MOSFET
IEEE Microwave and Wireless Components Letters, 2018, 28, 597-599
2.58Citations (PDF)
86NCFET Design Considering Maximum Interface Electric Field
IEEE Electron Device Letters, 2018, 39, 1254-1257
3.442Citations (PDF)
87Analysis and Modeling of Temperature and Bias Dependence of Current Mismatch in Halo-Implanted MOSFETs
IEEE Transactions on Electron Devices, 2018, 65, 3608-3616
2.714Citations (PDF)
88Anomalous Transconductance in Long Channel Halo Implanted MOSFETs: Analysis and Modeling
IEEE Transactions on Electron Devices, 2017, 64, 376-383
2.717Citations (PDF)
89A Predictive Tunnel FET Compact Model With Atomistic Simulation Validation
IEEE Transactions on Electron Devices, 2017, 64, 599-605
2.722Citations (PDF)
90Bulk FinFET With Low- $\kappa $ Spacers for Continued Scaling
IEEE Transactions on Electron Devices, 2017, 64, 1861-1864
2.755Citations (PDF)
91Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model
Japanese Journal of Applied Physics, 2017, 56, 04CD09
1.99Citations (PDF)
92Investigation of Mo/Ti/AlN/HfO2High-k Metal Gate Stack for Low Power Consumption InGaAs NMOS Device Application
IEEE Electron Device Letters, 2017, 38, 552-555
3.411Citations (PDF)
93Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect
IEEE Transactions on Microwave Theory and Techniques, 2017, 65, 2261-2270
3.619Citations (PDF)
94Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf0.8Zr0.2O2, High Endurance and Breakdown Recovery
IEEE Electron Device Letters, 2017, 38, 1379-1382
3.4100Citations (PDF)
95Compact Modeling Source-to-Drain Tunneling in Sub-10-nm GAA FinFET With Industry Standard Model
IEEE Transactions on Electron Devices, 2017, 64, 3576-3581
2.720Citations (PDF)
96Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs
IEEE Transactions on Electron Devices, 2017, 64, 3986-3990
2.714Citations (PDF)
97Stabilization of ferroelectric phase in tungsten capped Hf0.8Zr0.2O2
Applied Physics Letters, 2017, 111,
3.078Citations (PDF)
98High-gain monolithic 3D CMOS inverter using layered semiconductors
Applied Physics Letters, 2017, 111,
3.013Citations (PDF)
99Nanowire FET With Corner Spacer for High-Performance, Energy-Efficient Applications
IEEE Transactions on Electron Devices, 2017, 64, 5181-5187
2.731Citations (PDF)
100FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits
IEEE Electron Device Letters, 2017, 38, 16-19
3.447Citations (PDF)
101Impact of Parasitic Capacitance and Ferroelectric Parameters on Negative Capacitance FinFET Characteristics
IEEE Electron Device Letters, 2017, 38, 142-144
3.477Citations (PDF)
102Differential voltage amplification from ferroelectric negative capacitance
Applied Physics Letters, 2017, 111,
3.042Citations (PDF)
103Impact of Al content on InAs/AlSb/Al x Ga 1− x Sb tunnelling diode
Journal of Engineering, 2017, 2017, 403-406
0.60Citations (PDF)
104Modeling of Subsurface Leakage Current in Low Short Channel MOSFET at Accumulation Bias
IEEE Transactions on Electron Devices, 2016, 63, 1840-1845
2.714Citations (PDF)
105Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG
Microelectronics Journal, 2016, 56, 171-176
2.020Citations (PDF)
106Characterization of RF Noise in UTBB FD-SOI MOSFET
IEEE Journal of the Electron Devices Society, 2016, 4, 379-386
1.814Citations (PDF)
107Modeling of Charge and Quantum Capacitance in Low Effective Mass III-V FinFETs
IEEE Journal of the Electron Devices Society, 2016, 4, 396-401
1.815Citations (PDF)
108Study of Inherent Gate Coupling Nonuniformity of InAs/GaSb Vertical TFETs
IEEE Transactions on Electron Devices, 2016, 63, 4267-4272
2.79Citations (PDF)
109Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description
IEEE Transactions on Electron Devices, 2016, 63, 4981-4985
2.792Citations (PDF)
110Methods for Extracting Flat Band Voltage in the InGaAs High Mobility Materials
IEEE Electron Device Letters, 2016, 37, 1100-1103
3.48Citations (PDF)
111Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part II: Model Validation
IEEE Transactions on Electron Devices, 2016, 63, 4986-4992
2.7164Citations (PDF)
112FinFET With High-<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math> </inline-formula> Spacers for Improved Drive Current
IEEE Electron Device Letters, 2016, 37, 835-838
3.469Citations (PDF)
113RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model
IEEE Transactions on Microwave Theory and Techniques, 2016, 64, 1745-1751
3.636Citations (PDF)
114Monolithic 3D CMOS Using Layered Semiconductors
Advanced Materials, 2016, 28, 2547-2554
24.5151Citations (PDF)
115Effects of In-Situ Plasma-Enhanced Atomic Layer Deposition Treatment on the Performance of HfO2/In0.53Ga0.47As Metal-Oxide-Semiconductor Field-Effect Transistors
IEEE Electron Device Letters, 2016, , 1-1
3.421Citations (PDF)
116Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics
IEEE Transactions on Electron Devices, 2016, 63, 2197-2199
2.7198Citations (PDF)
117Analysis and modeling of flicker noise in lateral asymmetric channel MOSFETs
Solid-State Electronics, 2016, 115, 33-38
1.17Citations (PDF)
118Single crystal functional oxides on silicon
Nature Communications, 2016, 7,
13.7237Citations (PDF)
119Unified Compact Model Covering Drift-Diffusion to Ballistic Carrier Transport
IEEE Electron Device Letters, 2016, 37, 134-137
3.419Citations (PDF)
120Suppressing Non-Uniform Tunneling in InAs/GaSb TFET With Dual-Metal Gate
IEEE Journal of the Electron Devices Society, 2016, 4, 60-65
1.822Citations (PDF)
121Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor
IEEE Electron Device Letters, 2016, 37, 111-114
3.4223Citations (PDF)
122Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs
IEEE Journal of the Electron Devices Society, 2015, 3, 355-360
1.823Citations (PDF)
123Modeling SiGe FinFETs With Thin Fin and Current-Dependent Source/Drain Resistance
IEEE Electron Device Letters, 2015, 36, 636-638
3.48Citations (PDF)
124Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model
IEEE Journal of the Electron Devices Society, 2015, 3, 240-243
1.824Citations (PDF)
125Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support
IEEE Nanotechnology Magazine, 2015, 14, 580-584
2.122Citations (PDF)
126Modeling STI Edge Parasitic Current for Accurate Circuit Simulations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34, 1291-1294
1.712Citations (PDF)
127Piezoelectricity-Induced Schottky Barrier Height Variations in AlGaN/GaN High Electron Mobility Transistors
IEEE Electron Device Letters, 2015, 36, 902-904
3.430Citations (PDF)
128Capacitance Modeling in III–V FinFETs
IEEE Transactions on Electron Devices, 2015, 62, 3892-3897
2.731Citations (PDF)
129Simulation Study of a 3-D Device Integrating FinFET and UTBFET
IEEE Transactions on Electron Devices, 2015, 62, 83-87
2.734Citations (PDF)
130Modeling the impact of substrate depletion in FDSOI MOSFETs
Solid-State Electronics, 2015, 104, 6-11
1.129Citations (PDF)
131Modeling 20-nm Germanium FinFET With the Industry Standard FinFET Model
IEEE Electron Device Letters, 2014, 35, 711-713
3.421Citations (PDF)
132Modeling of GaN-Based Normally-Off FinFET
IEEE Electron Device Letters, 2014, 35, 612-614
3.441Citations (PDF)
133Two-dimensional to three-dimensional tunneling in InAs/AlSb/GaSb quantum well heterojunctions
Journal of Applied Physics, 2013, 114,
2.016Citations (PDF)
134(Invited) FinFET and UTB--How to Make Very Short Channel MOSFETs
ECS Transactions, 2013, 50, 17-20
0.411Citations (PDF)
135Interfacial layer reduction and high permittivity tetragonal ZrO2 on germanium reaching ultrathin 0.39 nm equivalent oxide thickness
Applied Physics Letters, 2013, 102,
3.016Citations (PDF)
136Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing
Applied Physics Letters, 2012, 100,
3.042Citations (PDF)
137BSIM-CG: A compact model of cylindrical/surround gate MOSFET for circuit simulations
Solid-State Electronics, 2012, 67, 79-89
1.129Citations (PDF)
138Random Telegraph Noise in 1X-nm CMOS Silicide Contacts and a Method to Extract Trap Density
IEEE Electron Device Letters, 2012, 33, 591-593
3.41Citations (PDF)
139Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights
IEEE Transactions on Electron Devices, 2012, 59, 2037-2041
2.744Citations (PDF)
140Competitive Oxidation During Buried Oxide Formation Using Separation by Plasma Implantation of Oxygen (Spimox)
Materials Research Society Symposia Proceedings, 2011, 388,
0.10Citations (PDF)
141Molybdenum as a Gate Electrode for Deep Sub-Micron CMOS Technology
Materials Research Society Symposia Proceedings, 2011, 611,
0.123Citations (PDF)
142Molybdenum Gate Electrode Technology For Deep Sub-Micron CMOS Generations
Materials Research Society Symposia Proceedings, 2011, 670,
0.17Citations (PDF)
143Dual Work Function CMOS Gate Technology Based on Metal Interdiffusion
Materials Research Society Symposia Proceedings, 2011, 670,
0.11Citations (PDF)
144Highly scaled (Lg∼56nm) gate-last Si tunnel field-effect transistors with ION>100μA/μm
Solid-State Electronics, 2011, 65-66, 22-27
1.116Citations (PDF)
145A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication
IEEE Transactions on Electron Devices, 2011, 58, 3678-3686
2.76Citations (PDF)
146A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates
Solid-State Electronics, 2011, 62, 31-39
1.125Citations (PDF)
147Ultrathin body InAs tunneling field-effect transistors on Si substrates
Applied Physics Letters, 2011, 98,
3.079Citations (PDF)
148Retraction notice to “Normalized mutual integral difference operator: A novel experimental method for extracting threshold voltage of MOSFETs” [Microelectron. J. 33 (2002) 667–670]
Microelectronics Journal, 2010, 41, 693
2.00Citations (PDF)
149Compact Modeling of Variation in FinFET SRAM Cells
IEEE Design and Test of Computers, 2010, 27, 44-50
0.225Citations (PDF)
150Tunnel Field Effect Transistor With Raised Germanium Source
IEEE Electron Device Letters, 2010, 31, 1107-1109
3.4161Citations (PDF)
151Air-Spacer MOSFET With Self-Aligned Contact for Future Dense Memories
IEEE Electron Device Letters, 2009, 30, 1368-1370
3.420Citations (PDF)
152Performance-Aware Corner Model for Design for Manufacturing
IEEE Transactions on Electron Devices, 2009, 56, 595-600
2.723Citations (PDF)
153Flicker-Noise Impact on Scaling of Mixed-Signal CMOS With HfSiON
IEEE Transactions on Electron Devices, 2008, 55, 417-422
2.711Citations (PDF)
154Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy
IEEE Transactions on Electron Devices, 2008, 55, 2657-2664
2.735Citations (PDF)
155Effect of Top Electrode Material on Resistive Switching Properties of $\hbox{ZrO}_{2}$ Film Memory Devices
IEEE Electron Device Letters, 2007, 28, 366-368
3.4317Citations (PDF)
156Modified resistive switching behavior of ZrO2 memory films based on the interface layer formed by using Ti top electrode
Journal of Applied Physics, 2007, 102,
2.0137Citations (PDF)
157MOSFET hot-carrier reliability improvement by forward-body bias
IEEE Electron Device Letters, 2006, 27, 605-608
3.432Citations (PDF)
158On gate leakage current partition for MOSFET compact model
Solid-State Electronics, 2006, 50, 1740-1743
1.11Citations (PDF)
159Novel dual-metal gate technology using Mo-MoSi/sub x/ combination
IEEE Transactions on Electron Devices, 2006, 53, 1420-1426
2.715Citations (PDF)
160MOSFET design for forward body biasing scheme
IEEE Electron Device Letters, 2006, 27, 387-389
3.438Citations (PDF)
161Bias Polarity Dependent Effects of>tex<$rm P+$>/tex
IEEE Transactions on Electron Devices, 2004, 51, 282-285
2.79Citations (PDF)
162Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs
Solid-State Electronics, 2004, 48, 969-978
1.135Citations (PDF)
163Characterization of Spatial Intrafield Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction
IEEE Transactions on Semiconductor Manufacturing, 2004, 17, 2-11
1.678Citations (PDF)
164MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations
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2.7215Citations (PDF)
165A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications
IEEE Transactions on Electron Devices, 2003, 50, 2408-2416
2.754Citations (PDF)
166Moore's law lives on [CMOS transistors]
IEEE Circuits and Devices: the Magazine of Electronic and Photonic Systems, 2003, 19, 35-42
0.234Citations (PDF)
167Practical compact modeling approaches and options for sub-0.1 μm CMOS technologies
Microelectronics Reliability, 2003, 43, 399-404
1.54Citations (PDF)
168Loop-based interconnect modeling and optimization approach for multigigahertz clock network design
IEEE Journal of Solid-State Circuits, 2003, 38, 457-463
3.627Citations (PDF)
169Improved a priori interconnect predictions and technology extrapolation in the GTX system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2003, 11, 3-14
1.910Citations (PDF)
170Frequency-independent equivalent-circuit model for on-chip spiral inductors
IEEE Journal of Solid-State Circuits, 2003, 38, 419-426
3.6325Citations (PDF)
171Extremely scaled silicon nano-CMOS devices
Proceedings of the IEEE, 2003, 9, 1860-1873
9.6237Citations (PDF)
172RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology
IEEE Electron Device Letters, 2003, 24, 251-253
3.49Citations (PDF)
173On the body-source built-in potential lowering of SOI MOSFETs
IEEE Electron Device Letters, 2003, 24, 90-92
3.412Citations (PDF)
174Direct tunneling RAM (DT-RAM) for high-density memory applications
IEEE Electron Device Letters, 2003, 24, 475-477
3.42Citations (PDF)
175Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion
IEEE Electron Device Letters, 2002, 23, 200-202
3.479Citations (PDF)
176Direct tunneling leakage current and scalability of alternative gate dielectrics
Applied Physics Letters, 2002, 81, 2091-2093
3.0198Citations (PDF)
177JVD silicon nitride as tunnel dielectric in p-channel flash memory
IEEE Electron Device Letters, 2002, 23, 91-93
3.420Citations (PDF)
178Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology
Journal of Applied Physics, 2002, 92, 7266-7271
2.0410Citations (PDF)
179A thermal activation view of low voltage impact ionization in MOSFETs
IEEE Electron Device Letters, 2002, 23, 550-552
3.437Citations (PDF)
180Effects of high-/spl kappa/ gate dielectric materials on metal and silicon gate workfunctions
IEEE Electron Device Letters, 2002, 23, 342-344
3.4163Citations (PDF)
181A capacitorless double-gate DRAM cell
IEEE Electron Device Letters, 2002, 23, 345-347
3.4120Citations (PDF)
182Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, 21, 544-553
1.7131Citations (PDF)
183Nanoscale CMOS spacer FinFET for the terabit era
IEEE Electron Device Letters, 2002, 23, 25-27
3.4159Citations (PDF)
184Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002, 10, 799-805
1.932Citations (PDF)
185Enhanced substrate current in SOI MOSFETs
IEEE Electron Device Letters, 2002, 23, 282-284
3.418Citations (PDF)
186An adjustable work function technology using Mo gate for CMOS devices
IEEE Electron Device Letters, 2002, 23, 49-51
3.4177Citations (PDF)
187Normalized mutual integral difference method to extract threshold voltage of MOSFETs
IEEE Electron Device Letters, 2002, 23, 428-430
3.420Citations (PDF)
188Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel
IEEE Transactions on Electron Devices, 2002, 49, 279-286
2.730Citations (PDF)
189A spacer patterning technology for nanoscale CMOS
IEEE Transactions on Electron Devices, 2002, 49, 436-441
2.7193Citations (PDF)
190A simple method for optimization of 6H-SiC punch-through junctions used in both unipolar and bipolar power devices
IEEE Transactions on Electron Devices, 2002, 49, 933-937
2.76Citations (PDF)
191Equivalent junction method to predict 3-D effect of curved-abrupt p-n junctions
IEEE Transactions on Electron Devices, 2002, 49, 1322-1325
2.758Citations (PDF)
192Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs
IEEE Transactions on Electron Devices, 2002, 49, 2288-2295
2.777Citations (PDF)
193Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era
Solid-State Electronics, 2002, 46, 1595-1601
1.154Citations (PDF)
194Efficient generation of pre-silicon MOS model parameters for early circuit design
IEEE Journal of Solid-State Circuits, 2001, 36, 156-159
3.611Citations (PDF)
195Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric
IEEE Electron Device Letters, 2001, 22, 227-229
3.4100Citations (PDF)
196Two silicon nitride technologies for post-SiO2 MOSFET gate dielectric
IEEE Electron Device Letters, 2001, 22, 324-326
3.411Citations (PDF)
197Hot-carrier reliability comparison for pMOSFETs with ultrathin silicon-nitride and silicon-oxide gate dielectrics
IEEE Transactions on Device and Materials Reliability, 2001, 1, 158-162
1.35Citations (PDF)
198Scaling CMOS devices through alternative structures
Science in China Series F: Information Sciences, 2001, 44, 1-7
0.42Citations (PDF)
199Charge-trap memory device fabricated by oxidation of Si/sub 1-x/Ge/sub x/
IEEE Transactions on Electron Devices, 2001, 48, 696-700
2.7223Citations (PDF)
200SOI thermal impedance extraction methodology and its significance for circuit simulation
IEEE Transactions on Electron Devices, 2001, 48, 730-736
2.7144Citations (PDF)
201Noise modeling and characterization for 1.5-V 1.8-GHz SOI low-noise amplifier
IEEE Transactions on Electron Devices, 2001, 48, 803-809
2.77Citations (PDF)
202Patterning sub-30-nm MOSFET gate with i-line lithography
IEEE Transactions on Electron Devices, 2001, 48, 1004-1006
2.733Citations (PDF)
203Optimization of sub-5-nm multiple-thickness gate oxide formed by oxygen implantation
IEEE Transactions on Electron Devices, 2001, 48, 1279-1281
2.76Citations (PDF)
204Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling
IEEE Transactions on Electron Devices, 2001, 48, 1366-1373
2.7298Citations (PDF)
205Dual work function metal gate CMOS technology using metal interdiffusion
IEEE Electron Device Letters, 2001, 22, 444-446
3.4171Citations (PDF)
206Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain
IEEE Electron Device Letters, 2001, 22, 447-448
3.447Citations (PDF)
207Intrinsic reliability projections for a thin JVD silicon nitride gate dielectric in P-MOSFET
IEEE Transactions on Device and Materials Reliability, 2001, 1, 4-8
1.38Citations (PDF)
208Sub-60-nm quasi-planar FinFETs fabricated using a simplified process
IEEE Electron Device Letters, 2001, 22, 487-489
3.4136Citations (PDF)
209MOSFET scaling into the 10 nm regime
Superlattices and Microstructures, 2000, 28, 351-355
4.717Citations (PDF)
210A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain
Superlattices and Microstructures, 2000, 28, 445-452
4.735Citations (PDF)
211FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
IEEE Transactions on Electron Devices, 2000, 47, 2320-2325
2.71,477Citations (PDF)
212Nanoscale ultra-thin-body silicon-on-insulator P-MOSFET with a SiGe/Si heterostructure channel
IEEE Electron Device Letters, 2000, 21, 161-163
3.447Citations (PDF)
213Polycrystalline silicon/metal stacked gate for threshold voltage control in metal–oxide–semiconductor field-effect transistors
Applied Physics Letters, 2000, 76, 1938-1940
3.02Citations (PDF)
214Ultrathin-body SOI MOSFET for deep-sub-tenth micron era
IEEE Electron Device Letters, 2000, 21, 254-255
3.4185Citations (PDF)
215Thermal characteristics of submicron vias studied by scanning Joule expansion microscopy
IEEE Electron Device Letters, 2000, 21, 224-226
3.426Citations (PDF)
216Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric
IEEE Electron Device Letters, 2000, 21, 540-542
3.4145Citations (PDF)
217A simple subcircuit extension of the BSIM3v3 model for CMOS RF design
IEEE Journal of Solid-State Circuits, 2000, 35, 612-624
3.655Citations (PDF)
218The prospect of process-induced charging damage in future thin gate oxides
Microelectronics Reliability, 1999, 39, 567-577
1.510Citations (PDF)
219Impact of time dependent dielectric breakdown and stress-induced leakage current on the reliability of high dielectric constant (Ba,Sr)TiO/sub 3/ thin-film capacitors for Gbit-scale DRAMs
IEEE Transactions on Electron Devices, 1999, 46, 342-347
2.731Citations (PDF)
220MOS capacitance measurements for high-leakage thin dielectrics
IEEE Transactions on Electron Devices, 1999, 46, 1500-1501
2.7470Citations (PDF)
221Channel width dependence of hot-carrier induced degradation in shallow trench isolated PMOSFETs
IEEE Transactions on Electron Devices, 1999, 46, 1532-1536
2.713Citations (PDF)
222Direct sampling methodology for statistical analysis of scaled CMOS technologies
IEEE Transactions on Semiconductor Manufacturing, 1999, 12, 403-408
1.625Citations (PDF)
223Observation of reduced boron penetration and gate depletion for poly-Si/sub 0.8/Ge/sub 0.2/ gated PMOS devices
IEEE Electron Device Letters, 1999, 20, 9-11
3.421Citations (PDF)
224A long-refresh dynamic/quasi-nonvolatile memory device with 2-nm tunneling oxide
IEEE Electron Device Letters, 1999, 20, 409-411
3.441Citations (PDF)
225Evidence of hole direct tunneling through ultrathin gate oxide using P/sup +/ poly-SiGe gate
IEEE Electron Device Letters, 1999, 20, 268-270
3.428Citations (PDF)
226Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages
IEEE Journal of Solid-State Circuits, 1999, 34, 85-89
3.650Citations (PDF)
227Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates
IEEE Journal of Solid-State Circuits, 1999, 34, 367-371
3.620Citations (PDF)
228Enhancement of PMOS device performance with poly-SiGe gate
IEEE Electron Device Letters, 1999, 20, 232-234
3.420Citations (PDF)
229Electromigration under time-varying current stress
Microelectronics Reliability, 1998, 38, 295-308
1.532Citations (PDF)
230A 0.1-μm delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy
IEEE Transactions on Electron Devices, 1998, 45, 809-814
2.763Citations (PDF)
231A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation
IEEE Transactions on Electron Devices, 1998, 45, 834-841
2.797Citations (PDF)
232Gate engineering for deep-submicron CMOS transistors
IEEE Transactions on Electron Devices, 1998, 45, 1253-1262
2.771Citations (PDF)
233Plasma immersion ion implantation for SOI synthesis: SIMOX and ion-cut
Journal of Electronic Materials, 1998, 27, 1059-1066
2.313Citations (PDF)
234Reliability phenomena under AC stress
Microelectronics Reliability, 1998, 38, 1-5
1.519Citations (PDF)
235Characterization of Global Inversion Layer in Thin-Gate-Oxide Deep-Submicron p-MOSFETs
Solid-State Electronics, 1998, 42, 401-404
1.11Citations (PDF)
236Plasma charging damage during over-etch time of aluminum
Solid-State Electronics, 1998, 42, 911-913
1.14Citations (PDF)
237Transistor characteristics with Ta/sub 2/O/sub 5/ gate dielectric
IEEE Electron Device Letters, 1998, 19, 441-443
3.4103Citations (PDF)
2380.35-μm asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology
IEEE Electron Device Letters, 1998, 19, 216-218
3.413Citations (PDF)
239Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics
IEEE Electron Device Letters, 1998, 19, 341-342
3.462Citations (PDF)
240Enhanced hot-carrier induced degradation in shallow trench isolated narrow channel PMOSFET's
IEEE Electron Device Letters, 1998, 19, 332-334
3.413Citations (PDF)
241Investigation of poly-Si/sub 1-x/Ge/sub x/ for dual-gate CMOS technology
IEEE Electron Device Letters, 1998, 19, 247-249
3.415Citations (PDF)
242Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation
IEEE Transactions on Components and Packaging Technologies, 1998, 21, 406-411
0.698Citations (PDF)
243Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation
IEEE Journal of Solid-State Circuits, 1998, 33, 449-453
3.677Citations (PDF)
244Performance and V/sub dd/ scaling in deep submicrometer CMOS
IEEE Journal of Solid-State Circuits, 1998, 33, 1586-1589
3.631Citations (PDF)
245A unified MOSFET channel charge model for device modeling in circuit simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998, 17, 641-644
1.722Citations (PDF)
246An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution
IEEE Transactions on Semiconductor Manufacturing, 1998, 11, 204-210
1.636Citations (PDF)
247Plasma charging damage on ultrathin gate oxides
IEEE Electron Device Letters, 1998, 19, 1-3
3.435Citations (PDF)
248Simulation of SOI devices and circuits using BSIM3SOI
IEEE Electron Device Letters, 1998, 19, 323-325
3.46Citations (PDF)
249A simple method for on-chip, sub-femto Farad interconnect capacitance measurement
IEEE Electron Device Letters, 1997, 18, 21-23
3.417Citations (PDF)
250AC output conductance of SOI MOSFETs and impact on analog applications
IEEE Electron Device Letters, 1997, 18, 36-38
3.415Citations (PDF)
251A MOSFET electron mobility model of wide temperature range (77 - 400 K) for IC simulation
Semiconductor Science and Technology, 1997, 12, 355-358
2.268Citations (PDF)
252Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scaling
IEEE Electron Device Letters, 1997, 18, 275-277
3.419Citations (PDF)
253Impact of nitrogen (N/sub 14/) implantation into polysilicon gate on high-performance dual-gate CMOS transistors
IEEE Electron Device Letters, 1997, 18, 312-314
3.419Citations (PDF)
254High-current failure model for VLSI interconnects under short-pulse stress conditions
IEEE Electron Device Letters, 1997, 18, 405-407
3.461Citations (PDF)
255Separation by plasma implantation of oxygen (SPIMOX) operational phase space
IEEE Transactions on Plasma Science, 1997, 25, 1128-1135
1.220Citations (PDF)
256Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI
IEEE Transactions on Electron Devices, 1997, 44, 414-422
2.7394Citations (PDF)
257A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation
IEEE Transactions on Electron Devices, 1997, 44, 277-287
2.7165Citations (PDF)
258Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's
IEEE Transactions on Electron Devices, 1997, 44, 627-634
2.7167Citations (PDF)
259High-field transport of inversion-layer electrons and holes including velocity overshoot
IEEE Transactions on Electron Devices, 1997, 44, 664-671
2.732Citations (PDF)
260Simulating process-induced gate oxide damage in circuits
IEEE Transactions on Electron Devices, 1997, 44, 1393-1400
2.710Citations (PDF)
261Overestimation of oxide defects density in large test capacitors due to plasma processing
IEEE Transactions on Electron Devices, 1997, 44, 1554-1556
2.76Citations (PDF)
262Optimizing quarter and sub-quarter micron CMOS circuit speed considering interconnect loading effects
IEEE Transactions on Electron Devices, 1997, 44, 1556-1558
2.73Citations (PDF)
263MOSFET inversion layer capacitance model based on Fermi-Dirac statistics for wide temperature range
Solid-State Electronics, 1997, 41, 507-509
1.13Citations (PDF)
264Modeling of small size MOSFETs with reverse short channel and narrow width effects for circuit simulation
Solid-State Electronics, 1997, 41, 1227-1231
1.117Citations (PDF)
265Comparison of GIDL in p/sup +/-poly PMOS and n/sup +/-poly PMOS devices
IEEE Electron Device Letters, 1996, 17, 285-287
3.415Citations (PDF)
266A full-process damage detection method using small MOSFET and protection diode
IEEE Electron Device Letters, 1996, 17, 563-565
3.412Citations (PDF)
267The impact of device scaling and power supply change on CMOS gate performance
IEEE Electron Device Letters, 1996, 17, 202-204
3.464Citations (PDF)
268Modeling and characterization of electromigration failures under bidirectional current stress
IEEE Transactions on Electron Devices, 1996, 43, 800-808
2.745Citations (PDF)
269Accelerated testing of SiO/sub 2/ reliability
IEEE Transactions on Electron Devices, 1996, 43, 70-80
2.762Citations (PDF)
270A novel self-aligned punchthrough implant: A simulation study
IEEE Transactions on Electron Devices, 1996, 43, 1312-1314
2.70Citations (PDF)
271A comparative study of advanced MOSFET concepts
IEEE Transactions on Electron Devices, 1996, 43, 1742-1753
2.7211Citations (PDF)
272Punchthrough diode as the transient voltage suppressor for low-voltage electronics
IEEE Transactions on Electron Devices, 1996, 43, 2037-2040
2.723Citations (PDF)
273Modeling of a MOSFET's parasitic resistance's narrow width and body bias effects for an IC simulator
Solid-State Electronics, 1996, 39, 1405-1408
1.15Citations (PDF)
274MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages
Solid-State Electronics, 1996, 39, 1515-1518
1.1110Citations (PDF)
275AC effects in IC reliability
Microelectronics Reliability, 1996, 36, 1611-1617
1.510Citations (PDF)
276Hot-carrier-induced degradation in ultra-thin-film fully-depleted SOI MOSFETs
Solid-State Electronics, 1996, 39, 1791-1794
1.110Citations (PDF)
277Circuit Reliability Simulation
Materials Research Society Symposia Proceedings, 1995, 391,
0.10Citations (PDF)
278An electro-thermal model for metal-oxide-metal antifuses
IEEE Transactions on Electron Devices, 1995, 42, 1548-1558
2.727Citations (PDF)
279ESD reliability and protection schemes in SOI CMOS output buffers
IEEE Transactions on Electron Devices, 1995, 42, 1816-1821
2.78Citations (PDF)
280Comparative study of fully depleted and body-grounded non fully depleted SOI MOSFETs for high performance analog and mixed signal circuits
IEEE Transactions on Electron Devices, 1995, 42, 1975-1981
2.729Citations (PDF)
281Simulating radiation reliability with BERT
Microelectronics Journal, 1995, 26, 627-633
2.02Citations (PDF)
282Bipolar transistor degradation under dynamic hot carrier stress
Solid-State Electronics, 1995, 38, 787-789
1.16Citations (PDF)
283Polysilicon gate depletion effect on IC performance
Solid-State Electronics, 1995, 38, 1975-1977
1.117Citations (PDF)
284An AC conductance technique for measuring self-heating in SOI MOSFET's
IEEE Electron Device Letters, 1995, 16, 67-69
3.461Citations (PDF)
285Modeling electromigration lifetime under bidirectional current stress
IEEE Electron Device Letters, 1995, 16, 476-478
3.419Citations (PDF)
286Thin dielectric degradation during silicon selective epitaxial growth process
Applied Physics Letters, 1995, 67, 2040-2042
3.06Citations (PDF)
287Electromigration characteristics of TiN barrier layer material
IEEE Electron Device Letters, 1995, 16, 230-232
3.412Citations (PDF)
288SOI/bulk hybrid technology on SIMOX wafers for high performance circuits with good ESD immunity
IEEE Electron Device Letters, 1995, 16, 11-13
3.410Citations (PDF)
289High-endurance ultra-thin tunnel oxide in MONOS device structure for dynamic memory application
IEEE Electron Device Letters, 1995, 16, 491-493
3.446Citations (PDF)
290Circuit-level simulation of TDDB failure in digital CMOS circuits
IEEE Transactions on Semiconductor Manufacturing, 1995, 8, 370-374
1.618Citations (PDF)
291Punchthrough transient voltage suppressor for low-voltage electronics
IEEE Electron Device Letters, 1995, 16, 303-305
3.414Citations (PDF)
292Simulation of deep submicron SOI N-MOSFET considering the velocity overshoot effect
IEEE Electron Device Letters, 1995, 16, 333-335
3.46Citations (PDF)
293Ultra-large-scale integration device scaling and reliability
Journal of Vacuum Science & Technology an Official Journal of the American Vacuum Society B, Microelectronics Processing and Phenomena, 1994, 12, 3237
1.517Citations (PDF)
294MOSFET saturation voltage
Solid-State Electronics, 1994, 37, 1445-1446
1.18Citations (PDF)
295An electromigration failure model for interconnects under pulsed and bidirectional current stressing
IEEE Transactions on Electron Devices, 1994, 41, 539-545
2.756Citations (PDF)
296Hot-carrier-reliability design rules for translating device degradation to CMOS digital circuit degradation
IEEE Transactions on Electron Devices, 1994, 41, 681-691
2.733Citations (PDF)
297Hole injection SiO/sub 2/ breakdown model for very low voltage lifetime extrapolation
IEEE Transactions on Electron Devices, 1994, 41, 761-767
2.7514Citations (PDF)
298Simulating the competing effects of P- and N-MOSFET hot-carrier aging in CMOS circuits
IEEE Transactions on Electron Devices, 1994, 41, 852-853
2.719Citations (PDF)
299Effects of temperature and defects on breakdown lifetime of thin SiO/sub 2/ at very low voltages
IEEE Transactions on Electron Devices, 1994, 41, 1227-1232
2.760Citations (PDF)
300New insight into high-field mobility enhancement of nitrided-oxide N-MOSFET's based on noise measurement
IEEE Transactions on Electron Devices, 1994, 41, 2205-2209
2.736Citations (PDF)
301Hot-carrier-reliability design guidelines for CMOS logic circuits
IEEE Journal of Solid-State Circuits, 1994, 29, 253-262
3.630Citations (PDF)
302Metal‐oxide‐semiconductor field‐effect‐transistor substrate current during Fowler–Nordheim tunneling stress and silicon dioxide reliability
Journal of Applied Physics, 1994, 76, 3695-3700
2.0132Citations (PDF)
303A complete radiation reliability software simulator
IEEE Transactions on Nuclear Science, 1994, 41, 2619-2630
1.316Citations (PDF)
304A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation
IEEE Electron Device Letters, 1994, 15, 510-512
3.4112Citations (PDF)
305Effect of low and high temperature anneal on process-induced damage of gate oxide
IEEE Electron Device Letters, 1994, 15, 475-476
3.468Citations (PDF)
306Plasma etching antenna effect on oxide-silicon interface reliability
Solid-State Electronics, 1993, 36, 1356-1358
1.122Citations (PDF)
307A bidirectional NMOSFET current reduction model for simulation of hot-carrier-induced circuit degradation
IEEE Transactions on Electron Devices, 1993, 40, 2245-2254
2.746Citations (PDF)
308Monitoring plasma-process induced damage in thin oxide
IEEE Transactions on Semiconductor Manufacturing, 1993, 6, 96-102
1.630Citations (PDF)
309Elimination of stress induced oxide leakage in textured tunneling oxide
Solid-State Electronics, 1992, 35, 1843-1844
1.10Citations (PDF)
310The Berkeley reliability simulator BERT: an IC reliability simulator
Microelectronics Journal, 1992, 23, 97-102
2.025Citations (PDF)
311Device-circuit mixed simulation of VDMOS charge transients
Solid-State Electronics, 1991, 34, 1353-1360
1.12Citations (PDF)
312Enhanced conductivity and breakdown of oxides grown on heavily implanted substrates
Solid-State Electronics, 1991, 34, 1207-1213
1.19Citations (PDF)
313A p-v-n diode model for CMOS latchup
Solid-State Electronics, 1991, 34, 1275-1279
1.14Citations (PDF)
314Oxide implantation for threshold voltage control
Solid-State Electronics, 1990, 33, 1447-1453
1.10Citations (PDF)
315GaAs MESFET model for circuit simulation
International Journal of Electronics, 1989, 66, 379-397
1.52Citations (PDF)
316Hot-carrier-induced MOSFET degradation under AC stress
IEEE Electron Device Letters, 1987, 8, 333-335
3.464Citations (PDF)
317The effects of thermal nitridation conditions on the reliability of thin nitrided oxide films
IEEE Electron Device Letters, 1987, 8, 143-145
3.432Citations (PDF)
318Ultra-thin silicon-dioxide breakdown characteristics of MOS devices with n+and p+polysilicon gates
IEEE Electron Device Letters, 1987, 8, 572-575
3.419Citations (PDF)
319Device characteristics of mosfets in MeV implanted substrates
Nuclear Instruments & Methods in Physics Research B, 1987, 21, 163-167
1.26Citations (PDF)
320Operation of CMOS devices with a floating well
IEEE Transactions on Electron Devices, 1987, 34, 335-343
2.721Citations (PDF)
32150-&amp;#197; gate-Oxide MOSFET's at 77 K
IEEE Transactions on Electron Devices, 1987, 34, 2129-2135
2.745Citations (PDF)
322Effects of substrate resistance on CMOS latchup holding voltages
IEEE Transactions on Electron Devices, 1987, 34, 2309-2316
2.711Citations (PDF)
323MOSFET drain breakdown voltage
IEEE Electron Device Letters, 1986, 7, 449-450
3.425Citations (PDF)
324An analytical model for the power bipolar-MOS transistor
Solid-State Electronics, 1986, 29, 1229-1237
1.142Citations (PDF)
325Residential time-of-use kilowatthour meter
Electric Power Systems Research, 1986, 11, 13-23
3.81Citations (PDF)
326Inversion-layer capacitance and mobility of very thin gate-Oxide MOSFET's
IEEE Transactions on Electron Devices, 1986, 33, 409-413
2.7145Citations (PDF)
327Optimization of epitaxial layers for power bipolar-MOS transistor
IEEE Electron Device Letters, 1986, 7, 510-512
3.410Citations (PDF)
328Hot-electron-induced MOSFET degradation&amp;#8212;Model, monitor, and improvement
IEEE Transactions on Electron Devices, 1985, 32, 375-385
2.7970Citations (PDF)
329Electrical breakdown in thin gate and tunneling oxides
IEEE Transactions on Electron Devices, 1985, 32, 413-422
2.7476Citations (PDF)
330Quantum yield of electron impact ionization in silicon
Journal of Applied Physics, 1985, 57, 302-309
2.0173Citations (PDF)
331Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement
IEEE Journal of Solid-State Circuits, 1985, 20, 295-305
3.6277Citations (PDF)
332Electrical Breakdown in Thin Gate and Tunneling Oxides
IEEE Journal of Solid-State Circuits, 1985, 20, 333-342
3.694Citations (PDF)
333Optimum design of power MOSFET's
IEEE Transactions on Electron Devices, 1984, 31, 1693-1700
2.784Citations (PDF)
334A compact IGFET charge model
IEEE Transactions on Circuits and Systems, 1984, 31, 745-748
1.233Citations (PDF)
335Lucky-electron model of channel hot-electron injection in MOSFET'S
IEEE Transactions on Electron Devices, 1984, 31, 1116-1125
2.7270Citations (PDF)
336Substrate resistance calculation for latchup modeling
IEEE Transactions on Electron Devices, 1984, 31, 1152-1155
2.78Citations (PDF)
337MOSFET degradation due to stressing of thin oxide
IEEE Transactions on Electron Devices, 1984, 31, 1238-1244
2.7122Citations (PDF)
338Hot-electron-induced photon and photocarrier generation in Silicon MOSFET's
IEEE Transactions on Electron Devices, 1984, 31, 1264-1273
2.7304Citations (PDF)
339A simplified model of short-channel MOSFET characteristics in the breakdown mode
IEEE Transactions on Electron Devices, 1983, 30, 571-576
2.730Citations (PDF)
340A simple punchthrough model for short-channel MOSFET's
IEEE Transactions on Electron Devices, 1983, 30, 1354-1359
2.721Citations (PDF)
341The operation of power MOSFET in reverse mode
IEEE Transactions on Electron Devices, 1983, 30, 1825-1828
2.710Citations (PDF)
342Optimum doping profile of power MOSFET epitaxial layer
IEEE Transactions on Electron Devices, 1982, 29, 985-987
2.721Citations (PDF)
343Second breakdown of vertical power MOSFET's
IEEE Transactions on Electron Devices, 1982, 29, 1287-1293
2.738Citations (PDF)
344An analytical breakdown model for short-channel MOSFET's
IEEE Transactions on Electron Devices, 1982, 29, 1735-1740
2.7107Citations (PDF)
345Correlation between substrate and gate currents in MOSFET's
IEEE Transactions on Electron Devices, 1982, 29, 1740-1744
2.755Citations (PDF)
346Errors in threshold-voltage measurements of MOS transistors for dopant-profile determinations
Solid-State Electronics, 1981, 24, 313-316
1.111Citations (PDF)
347Correction to "Determination of nonuniform diffusion length and electric field in semiconductors"
IEEE Transactions on Electron Devices, 1979, 26, 162-162
2.70Citations (PDF)
348Optimum doping profile for minimum ohmic resistance and high-breakdown voltage
IEEE Transactions on Electron Devices, 1979, 26, 243-244
2.7110Citations (PDF)
349Determination of diffusion length and surface recombination velocity by light excitation
Solid-State Electronics, 1978, 21, 965-968
1.135Citations (PDF)
350Determination of nonuniform diffusion length and electric field in semiconductors
IEEE Transactions on Electron Devices, 1978, 25, 822-825
2.74Citations (PDF)
351LED charge-control model and speed at high currents
Proceedings of the IEEE, 1978, 66, 599-601
9.61Citations (PDF)
352Liquid-crystal waveguides for integrated optics
IEEE Journal of Quantum Electronics, 1977, 13, 262-267
1.358Citations (PDF)
353Analysis of silicon solar cells with stripe geometry junctions
Solid-State Electronics, 1977, 20, 119-123
1.12Citations (PDF)
354Field-dependent light scattering in nematic liquid crystals
Proceedings of the IEEE, 1976, 64, 1737-1738
9.63Citations (PDF)
355Electrooptic modulation in grain-oriented ZnO films
IEEE Journal of Quantum Electronics, 1975, 11, 886-886
1.30Citations (PDF)
356Optical deflection in thin-film nematic-liquid-crystal waveguides
IEEE Journal of Quantum Electronics, 1974, 10, 218-222
1.310Citations (PDF)
357Losses of a nematic liquid-crystal optical waveguide*
Journal of the Optical Society of America, 1974, 64, 1424
1.257Citations (PDF)
358Field-realigned nematic-liquid-crystal optical waveguides
IEEE Journal of Quantum Electronics, 1974, 10, 556-562
1.310Citations (PDF)
359Liquid crystals in integrated optics
IEEE Journal of Quantum Electronics, 1973, 9, 684-685
1.30Citations (PDF)
360New Thermooptical Measurement Method and a Comparison with Other Methods
Applied Optics, 1973, 12, 72
1.8301Citations (PDF)
361A resistive-gated IGFET tetrode
IEEE Transactions on Electron Devices, 1971, 18, 418-425
2.74Citations (PDF)
362Physics-Enhanced Neural Network Compact Model for Fast and Flexible Transistor Modeling
IEEE Transactions on Electron Devices, 0, 72, 6487-6493
2.72Citations (PDF)
363Nonlinear Body Resistance in SOI MOSFETs Under Dynamic Depletion: Compact Modeling and DC Characterization
IEEE Transactions on Electron Devices, 0, 73, 1155-1162
2.70Citations (PDF)
364Demonstration of Near Ideal Short Channel Effect in L g = 25-nm Gate-All-Around Transistors Using Negative Capacitance Gate Stack
IEEE Electron Device Letters, 0, 47, 434-437
3.40Citations (PDF)
365Physics-Informed Neural Networks for Device and Circuit Modeling: A Case Study of NeuroSPICE
IEEE Electron Device Letters, 0, 47, 1021-1024
3.41Citations (PDF)